Area-Efficient Pipelined FFT Processor for Zero-Padded Signals
نویسندگان
چکیده
منابع مشابه
An Efficient Pipelined FFT Processor for OFDM Communication Systems
Increasing speeds and complexity of wireless communication systems have necessitated the progress and advancement of high performance signal processing elements. Today's emerging technologies require fast processing and efficient use of resources. These resources include power, memory, and chip area. Ongoing research seeks to optimize resource usage as well as performance. Design becomes a bala...
متن کاملEfficient Detection of Zero-padded Ofdm Signals with Large Blocks
In this paper, we present a frequency-domain receiver for ZP-OFDM schemes (Zero-Padded Orthogonal Frequency Division Multiplexing) where the duration of the channel impulse response is a significant fraction of the duration of the OFDM block. The proposed receiver has a relatively low complexity, allowing an FFT-based (Fast Fourier Transform) implementation. The proposed receiver is suitable to...
متن کاملArea-efficient FFT processor for MIMO-OFDM based SDR systems
In this letter, an area-efficient FFT processor is proposed for MIMO-OFDM based SDR systems. The proposed FFT processor can support variable lengths of 64, 128, 256, 512, 1024, 1536 and 2048. By reducing the required number of non-trivial multipliers with a mixed-radix algorithm, the complexity of the proposed FFT processor is dramatically decreased. The proposed FFT processor was designed in a...
متن کاملA Low Power Pipelined FFT/IFFT Processor for OFDM Applications
To produce multiple subcarriers orthogonal frequency division multiplexing (OFDM) often require an inverse fast Fourier transform (IFFT).This paper, present the efficient implementation of a pipeline FFT/IFFT processor for OFDM applications. This design adopts a single-path delay feedback style as the proposed hardware architecture. To eliminate the read-only memories (ROM’s) used to store the ...
متن کاملHigh Performance Pipelined Design for FFT Processor based on FPGA
It is important to develop a high-performance FFT processor to meet the requirements of real time and low cost in many different systems. So a radix-2 pipelined FFT processor based on Field Programmable Gate Array (FPGA) for Wireless Local Area Networks (WLAN) is proposed. Unlike being stored in the traditional ROM, the twiddle factors in our pipelined FFT processor can be accessed directly. Th...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: Electronics
سال: 2019
ISSN: 2079-9292
DOI: 10.3390/electronics8121397